1. Field of the Invention
The present invention relates to a dielectric isolated type semiconductor device, and more particularly to a device integrating such a bipolar element as a bipolar transistor or the like.
2. Description of the Related Arts
In a bipolar integrated circuit integrating bipolar transistors, it is important to electrically isolate the elements from each other. As the isolation method, PN junctions are generally used. In case of, for instance, an NPN type bipolar transistor, an N type epitaxial layer formed on a P type substrate is partitioned by a P type diffusion layer to construct an island of a number of N type regions isolated from each other by PN junctions and to form a bipolar transistor in the N type island. For providing electrical isolation between the elements and between the elements and the substrate using this structure, the PN junctions formed between them are maintained in their reverse bias conditions. However, for preventing lowering of a withstand voltage, there is a problem that at a plane size of the bipolar transistor may not be made small. Namely, to make the element size small, it is necessary to shorten a distance from a diffusion region of an element to an isolation region, namely a P type isolation region. However, there is a probrem that the withstand voltage lowers when the distance to the isolation region is shortened, as shown in FIG. 28.
Therefore, a dielectric isolation method for isolating elements using insulating material such as a silicon oxide film or the like is known. This is a method in which an N type silicon layer is disposed on an insulation layer, the identical N type silicon layer is partitioned to form a plurality of N type silicon islands, an insulation film such as a silicon oxide film or the like is formed around the N type silicon island, and a circuit element is formed in the N type silicon island. With this method, as shown in FIG. 28, it is possible to maintain a high withstand voltage even if the distance to the isolation region is made small. In other words, it is possible to maintain the withstand voltage and also to make the element size small.
However, in the bipolar integrated circuit given by this dielectric isolation method it has been apparent that a switching time of the bipolar transistor has become slow.